1. Field of the Disclosure
The disclosure generally relates to a NAND flash memory device and to a method of forming a well of the NAND flash memory device, and more particularly, to a well formed in a cell region of a NAND flash memory device.
2. Brief Description of Related Technology
Generally, in a NAND flash memory device, a cell is erased through a F-N tunneling phenomenon. The NAND flash memory cell is formed on a single P well. A number of the cells are constructed in a string shape to form a cell string. A number of the cell strings are arranged in the longitudinal or lateral direction to form a cell block. Accordingly, an erase operation is performed by the cell block.
FIGS. 1A and 1B are conceptual views shown to explain a conventional erase operation. Referring to FIGS. 1A and 1B, a voltage of 0V is applied to a word line W/L of a selected cell block through a string select transistor SSL. A word line W/L of a non-selected cell block is floated through the string select transistor SSL. If a high voltage is applied to a P well, the cell is erased since a voltage difference between a gate electrode and a well of a memory cell within the selected cell block is too great (see FIG. 1A) and the gate electrode of the memory cell within the non-selected cell block is boosted to reduce the voltage difference between the word line W/L and the well. The cell is thus not erased (see FIG. 1B).
However, since a voltage of 20V or more is generally applied to the P well, the non-selected cell block also undergoes stress due to the same bias. Further, there exists the leakage current due to a string select transistor for floating the word line of the non-selected cell block. The word line of the non-selected cell block does not keep floated due to this leakage. As a result, there is a problem in that the status of data is not kept since a shallow erase phenomenon occurs. In addition, there is a problem in that specifications of a target device are not met because erase disturbance is caused.